Hiển thị các bài đăng có nhãn cmos. Hiển thị tất cả bài đăng
Hiển thị các bài đăng có nhãn cmos. Hiển thị tất cả bài đăng

Thứ Tư, 21 tháng 1, 2015

Continuous-Time Digital Front-Ends for Multistandard Wireless Transmission

Continuous-Time Digital Front-Ends for Multistandard Wireless Transmission



This book describes the design of fully digital multistandard transmitter front-ends which can directly drive one or more switching power amplifiers, thus eliminating all other analog components. After reviewing different architectures, the authors focus on polar architectures using pulse width modulation (PWM), which are entirely based on unclocked delay lines and other continuous-time digital hardware. As a result, readers are enabled to shift accuracy concerns from the voltage domain to the time domain, to coincide with submicron CMOS technology scaling. The authors present different architectural options and compare them, based on their effect on the signal and spectrum quality. Next, a high-level theoretical analysis of two different PWM-based architectures baseband PWM and RF PWM is made. On the circuit level, traditional digital components and design techniques are revisited from the point of view of continuous-time digital circuits. Important design criteria are identified and different solutions are presented, along with their advantages and disadvantages. Finally, two chips designed in nanometer CMOS technologies are described, along with measurement results for validation.




Thứ Sáu, 16 tháng 1, 2015

Advanced Gate Stacks for High-Mobility Semiconductors

Advanced Gate Stacks for High-Mobility Semiconductors



Will nanoelectronic devices continue to scale according to Moores law? At this moment, there is no easy answer since gate scaling is rapidly emerging as a serious roadblock for the evolution of CMOS technology. Channel engineering based on high-mobility semiconductor materials (e.g. strained Si, alternative orientation substrates, Ge or III-V compounds) could help overcome the obstacles since they offer performance enhancement. There are several concerns though. Do we know how to make complex engineered substrates (e.g. Germanium-on-Insulator)? Which are the best interface passivation methodologies and (high-k) gate dielectrics on Ge and III-V compounds? Can we process these materials in short channel transistors using flows, toolsets and know how similar to that in Si technology? How do these materials and devices behave at the nanoscale? The reader will get a clear view of what has been done so far, what is the state-of-the-art and which are the main challenges ahead before we come any close to a viable Ge and III-V MOS technology.